For advanced sub-micron semiconductor integrated circuit fabrication process technology, it is common to add filling material to each critical layer in an integrated circuit. The filling material added to a layer is usually of the same type of material as that used in the layer. For example, if the layer comprises interconnects, then the filling material is the same type of metal as the interconnects.
To planarize the interconnects, CMP (Chemical Mechanical Polishing) is often used during the fabrication process. The CMP process depends on the layout topology, such as for example the metal density and width. The filling material is usually required to achieve the desired density range for each layer in which filling material is added, which helps improve the CMP process window. However, the added filling material, which is usually in the shape of rectangles or polygons, may introduce extra RC (Resistance-Capacitance product) parasitics. Subsequently, this may negatively impact the timing and performance of the resulting integrated circuit.